GENERAL DESCRIPTION
128Mb Mobile LPDDR W947D6HB / Consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. By setting programmable Mode Registers, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). 2. FEATURES
VDD = 1.7~1.95V VDDQ = 1.7~1.95V; Data width: x16 / x32 Clock rate: 200MHz(-5),166MHz(-6),133MHz(-75) Partial Array Self-Refresh(PASR) Auto Temperature Compensated Self-Refresh(ATCSR) Power Down Mode Deep Power Down Mode (DPD Mode) Programmable output buffer driver strength Four internal banks for concurren...