Winbond Electronics Corporation W955N8MBYA
The master device has a separate CS# for each slave. The clock is not required to be free-running.| Part No. | W955N8MBYA |
|---|---|
| Datasheet | W955N8MBYA Download |
| Manufacturer |  Winbond Electronics Corporation |
| Description | 32Mb HyperRAM |
| Buy | Stock & Price |
FEATURES
● Interface: HyperBus● Power supply: 2.7V~3.6V
● Maximum clock rate: 200MHz
● Double-Data Rate (DDR) Up to 400 MT/s
● Clock: – Single ended clock (CK) – Differential clock (CK/CK#)
● Chip Select (CS#)
● 8-bit data bus (DQ[7:0])
● Hardware reset (RESET#)
● Read-Write Data Strobe (RWDS) – Bidirectional Data Strobe / Mask – Output at the start of all transactions to indicate refresh latency – Output during read transactions as Read Data Strobe – Input during write transactions as Write Data Mask Performance and Power
● Configurable output drive strength
● Power Saving Modes – Hybrid Sleep Mode – Deep Power Down
● Configurable Burst Characteristics – Linear burst – Wrapped burst lengths: – 16 bytes (8 clocks) – 32 bytes (16 clocks) – 64 bytes (32 clocks) – 128 bytes (64 clocks) – Hybrid burst - one wrapped burst followed by linear burst
● Array Refresh Modes – Full Array Refresh – Partial Array Refresh
● Support package: 24 balls TFBGA
● Operating temperature range: -40°C ≤ TCASE ≤ 85°C 2.
