GENERAL DESCRIPTION
The -25 is compliant to the DDR2-800 (6-6-6) specification, the -3 is compliant to the DDR2-667 (5-5-5) specification. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion. 2. FEATURES
z Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V z Double Data Rate architecture: two data transfers per clock cycle z CAS Latency: 3, 4, 5 and 6 z Burst Length: 4 and 8 z Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data z Edge-aligned with Read data and center-aligned with Write data z DLL aligns DQ and DQS transitions with clock z Differential clock inputs (CLK and CLK ) z Data masks (DM) for write data z Commands entered on each positive CLK edge, data and data mask are referenced to both...