Winbond Electronics Corporation W97BH2KB
The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.| Part No. | W97BH2KB |
|---|---|
| Datasheet | W97BH2KB Download |
| Manufacturer |  Winbond Electronics Corporation |
| Description | high-speed SDRAM |
| Buy | Stock & Price |
GENERAL DESCRIPTION
LPDDR2 is a high-speed SDRAM device internally configured as an 8-Bank memory. These devices contains 2 Gb has 2,147,483,648 bits. All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. 2.FEATURES
● VDD1 = 1.7~1.95V● VDD2/VDDCA/VDDQ = 1.14V~1.30V
● Data width: x16 / x32
● Clock rate: up to 533 MHz
● Data rate: up to 1066 Mb/s/pin
● Four-bit prefetch DDR architecture
● Eight internal banks for concurrent operation
● Programmable READ and WRITE latencies (RL/WL)
● Programmable bur...
