GENERAL DESCRIPTION
It is available in two organizations: 4,194,304-words × 4 banks × 32 bits or 8,388,608 words × 4 banks × 16 bits. The device operates in a fully synchronous mode, and the output data are synchronized to positive edges of the system clock and is capable of delivering data at clock rate up to 166MHz. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile game consoles and other handheld applications where large memory density and low power consumption are required. The device operates from 1.8V power supply, and supports the 1.8V LVCMOS bus interface. 2. FEATURES
Power supply VDD = 1.7V~1.95V VDDQ = 1.7V~1.95V Frequency : 166MHz(-6),133MHz(-75) Programmable Partial Array Self Refresh Power Down Mode Deep Power Down Mode (DPD) Programmable output buffer driver strength Automatic Te...