XC Memory GDQ2BFAC
DDR4 SDRAM
| Part No. | GDQ2BFAC |
|---|---|
| Datasheet | GDQ2BFAC Download |
| Manufacturer | XC Memory |
| Description | DDR4 SDRAM |
| Buy | Stock & Price |
FEATURES
● Power supply: VDD=VDDQ=1.2V (1.14V~1.26V); VPP=2.5V (2.375V~2.75V)● JEDEC standard package: 96-Ball FBGA (x16)
● Array Configuration: 8 Banks (x16) 2 groups of 4 banks
● 8n-Bit prefetch architecture
● Burst Length (BL): 8 and 4 with Burst Chop (BC)
● Programmable CAS Latency (CL)
● Programmable CAS Write Latency (CWL)
● Internal generated VREF for data inputs
● Data Mask (DM) for write data
● On-Die Termination (ODT): Support Nominal, Park and Dynamic ODT
● Interface: 1.2V Pseudo Open Drain (POD) IO
● Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)
● Per DRAM Addressability (PDA)
● Data Bus Inversion (DBI)
● Asynchronous reset for power up
● Maximum Power Saving Mode (MPSM)
● Precharge: Auto precharge option for each burst access
● Operating case temperature: -40°C≤TCASE≤95°C
● Support auto-refresh and self-refresh mode
● Low-power auto self refresh (LPASR)
● Temperature controlled refresh (TCR)
● Self refresh abort
● Average Refresh Period: - 7.8us at...
