XC6VCX130T Datasheet | Xilinx

Description Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, PCI Express® (GEN 1) patible integrated blocks, a tri-mode Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains Select IO™ technology with built-in digitally controlled impedance, Chip Sync™ source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware ponents to enable designers to focus on innovation as soon as their development cycle begins. Summary of Virtex-6 CXT FPGA Features - Advanced, high-performance, FPGA Logic - Real 6-input look-up table (LUT) technology - Dual LUT5 (5-input LUT) option - LUT/dual flip-flop pair for applications requiring rich register mix - Improved routing efficiency - 64-bit (or 32 x 2-bit) distributed LUT RAM option - SRL32/dual SRL16 with registered outputs option - Powerful mixed-mode clock managers (MMCM) - MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division - 36-Kb block RAM/FIFOs - Dual-port RAM blocks - Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits -...