Xicor X68C64
The X68C64 is an 8K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X68C64 features a Multiplexed Address and Data bus allowing a direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry. The X68C64 is internally configured as two independent 4K x 8 memory arrays.| Part No. | X68C64 |
|---|---|
| Datasheet | X68C64 Download |
| Manufacturer |  Xicor |
| Description | E2 Micro-Peripheral |
| Buy | Stock & Price |
DESCRIPTION
8192 x 8 BitFEATURES
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● CONCURRENT READ WRITE™ —Dual Plane Architecture —Isolates Read/Write Functions Between Planes —Allows Continuous Execution of Code From One Plane While Writing in the Other Plane Multiplexed Address/Data Bus —Direct Interface to Popular 8-bit Microcontrollers, e.g., Motorola M6801/03, M68HC11 Family High Performance CMOS —Fast Access Time, 120ns —Low Power —60mA Maximum Active —500µA Maximum Standby Software Data Protection Block Protect Register —Individually Set Write Lock Out in 1K Blocks Toggle Bit Polling —Early End of Write Detection Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle High Reliability —Endurance: 100,000 Write Cycles —Data Retention: 100 Years This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array; effectively eliminating the need for an auxiliary memory device for code storage. To write to the X68C64, a three-byte command sequence must precede the byte(s) being written.
