Datasheet Details
| Part number | SC9500XV |
|---|---|
| Manufacturer | Xilinx (now AMD) |
| File Size | 173.40 KB |
| Description | XC9500XV Family High-Performance CPLD |
| Datasheet |
 SC9500XV Datasheet
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General Description
Each XC9500XV device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT II switch matrix.
The IOB provides buffering for device inputs and outputs.
Key Features
- Optimized for high-performance 2.5V systems.
- 3.5 ns pin-to-pin logic delays Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) Lower power operation Multi-voltage operation FastFLASH technology In-system programmable Output banking (XC95144XV, XC95288XV) Superior pin-locking and routability with FastCONNECT II™ switch matrix Extra wide 54-input Function Blocks Up to 90 product-terms per macrocell with individual product-term allocation Loca.