4FG676I Datasheet | Xilinx

Features - - Industry First Platform FPGA Solution IP-Immersion™ Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O (Advance Data) Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz pliance, and Card Bus pliant - Differential Signaling - 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers - Bus LVDS I/O - Lightning Data Transport (LDT) I/O with current driver buffers - Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O - Built-in DDR Input and Output registers - Proprietary high-performance Select Link™ Technology - High-bandwidth data path - Double Data Rate (DDR) link - Web-based HDL generation methodology Supported by Xilinx Foundation™ and Alliance™ Series Development Systems - Integrated VHDL and Verilog design flows - pilation of 10M system gates designs - Internet Team Design (ITD) tool SRAM-Based In-System Configuration - Fast Select MAP™ configuration - Triple Data Encryption Standard (DES) security option (Bitstream Encryption) - IEEE1532 support - Partial reconfiguration - Unlimited re-programmability - Readback capability 0.15 µm 8-Layer Metal process with 0.12 µm high-speed transistors 1.5 V (VCCINT) core power supply, dedicated 3.3 V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 patible boundary-scan logic support Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in three standard fine pitches (0.80mm, 1.00mm, and 1.27mm) 100% factory tested Select RAM™ Memory Hierarchy - 3 Mb of True Dual-Port™ RAM in 18-Kbit block .. Select RAM resources - Up to 1.5 Mb of distributed Select RAM resources - High-performance interfaces to external memory - DDR-SDRAM interface - FCRAM interface - QDR™-SRAM interface - Sigma RAM interface - Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains - Flexible Logic Resources...