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XC17V00 - Configuration PROM

Description

Xilinx introduces

Features

  • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGA devices.
  • Simple interface to the FPGA.
  • Cascadable for storing longer or multiple bitstreams.
  • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions.
  • Low-power CMOS floating-gate process.
  • 3.3V supply voltage.
  • Guaranteed 20 year life data retention Product Specification.
  • Ava.

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — 0 R XC17V00 Series Configuration PROMs DS073 (v2.0) April 7, 2014 08 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGA devices • Simple interface to the FPGA • Cascadable for storing longer or multiple bitstreams • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • Low-power CMOS floating-gate process • 3.
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