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XC2C384 Datasheet PDF

Xilinx XC2C384

The CoolRunner-II 384-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices.
Part No. XC2C384
Datasheet XC2C384 Download
Manufacturer
Xilinx
Description CoolRunner-II CPLD
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XC2C384 datasheet page 1 preview

FEATURES

● Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current
● Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V
● Available in multiple package options - 144-pin TQFP with 118 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.0mm) BGA with 240 user I/O - Pb-free available for all packages
● Advanced system features - Fastest in system programming
● 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management
● DataGATE enable (DGE) signal control - Four separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes
● Optional DualEDGE triggered registers
● Clock divider (divide by 2,4,6,8,10,12,14,16)
● CoolCLOCK - Global signal options with macrocell control
● Multiple gl...
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