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XC2C512 - Coolrunner-ii CPLD

This page provides the datasheet information for the XC2C512, a member of the XC2C512_Xilinx Coolrunner-ii CPLD family.

Datasheet Summary

Description

The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications.

This lends power savings to high-end communication equipment and high speed to battery operated devices.

Features

  • Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current.
  • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation.
  • 1.5V to 3.3V.
  • Available in multiple package options - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.0mm) BGA with 270 user I/O - Pb-free available for all packages.
  • Advanced system f.

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Datasheet preview – XC2C512

Datasheet Details

Part number XC2C512
Manufacturer Xilinx
File Size 272.47 KB
Description Coolrunner-ii CPLD
Datasheet download datasheet XC2C512 Datasheet
Additional preview pages of the XC2C512 datasheet.

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Full PDF Text Transcription

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0 R XC2C512 CoolRunner-II CPLD DS096 (v3.2) March 8, 2007 00 Features • Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V • Available in multiple package options - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.0mm) BGA with 270 user I/O - Pb-free available for all packages • Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.
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