XC2C512
Description
The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications.
Key Features
- Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current
- Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation - 1.5V to 3.3V
- Advanced system features - Fastest in system programming
- DataGATE enable signal control - Four separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes
- Optional DualEDGE triggered registers
- Clock divider (divide by 2,4,6,8,10,12,14,16)
- CoolCLOCK - Global signal options with macrocell control
- Multiple global clocks with phase selection per macrocell
- Multiple global output enables
- Global set/reset - Advanced design security - PLA architecture
