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XC2S300E - Spartan-IIE FPGA

This page provides the datasheet information for the XC2S300E, a member of the XC2S50E Spartan-IIE FPGA family.

Datasheet Summary

Description

DS077-2 (v3.0) August 9, 2013 Architectural Description - Spartan-IIE Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan Development System Configuration Module 3: DC and Switching Characteristics D

Features

  • General Overview.
  • Product Availability.
  • User I/O Chart.
  • Ordering Information Module 2: Functional.

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Datasheet preview – XC2S300E

Datasheet Details

Part number XC2S300E
Manufacturer Xilinx
File Size 4.31 MB
Description Spartan-IIE FPGA
Datasheet download datasheet XC2S300E Datasheet
Additional preview pages of the XC2S300E datasheet.

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Full PDF Text Transcription

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — 0 R Spartan-IIE FPGA Family Data Sheet DS077 August 9, 2013 0 0 Product Specification This document includes all four modules of the Spartan®-IIE FPGA data sheet. Module 1: Introduction and Ordering Information DS077-1 (v3.0) August 9, 2013 • Introduction • Features • General Overview • Product Availability • User I/O Chart • Ordering Information Module 2: Functional Description DS077-2 (v3.0) August 9, 2013 • Architectural Description - Spartan-IIE Array - Input/Output Block - Configurable Logic Block - Block RAM - Clock Distribution: Delay-Locked Loop - Boundary Scan • Development System • Configuration Module 3: DC and Switching Characteristics DS077-3 (v3.
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