XC3100L Datasheet | Xilinx

Description - plete Development System - Schematic capture, automatic place and route - Logic and timing simulation - Interactive design editor for design optimization - Timing calculator - Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others Features - plete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and other PLD logic - Integrates plete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns - System clock speeds over 85 MHz - Low quiescent and active power consumption Flexible FPGA architecture - patible arrays ranging from 1,000 to 7,500 gate plexity - Extensive register, binatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Unlimited reprogrammability - Easy design iteration - In-system logic changes Extensive packaging options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Device XC3020A, 3020L, 3120A XC3030A, 3030L, 3130A XC3042A, 3042L, 3142A, 3142L XC3064A, 3064L, 3164A XC3090A, 3090L, 3190A, 3190L XC3195A Max Logic Gates 1,500 2,000 3,000 4,500 6,000 7,500 Typical Gate CLBs Range 1,000 - 1,500 64 1,500 - 2,000 2,000 - 3,000 3,500 - 4,500 5,000 - 6,000 6,500 - 7,500 100 144 224 320 484 - Additional XC3100A Features - Ultra-high-speed FPGA family with six members - 50-85 MHz system clock...