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XC7336 - 36-Macrocell CMOS EPLD

Key Features

  • High-performance Erasable Programmable Logic Devices (EPLDs).
  • 5 / 7.5 ns pin-to-pin speeds on all fast inputs.
  • Up to 167 MHz maximum clock frequency.
  • Advanced Dual-Block architecture.
  • Fast Function Blocks.
  • High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144).
  • 100% interconnect matrix.
  • High-speed arithmetic carry network.
  • 1 ns ripple-carry delay per bit.
  • 43 to 61 MHz 18-bit accumulators.

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® XC7300 CMOS EPLD Family Product Description Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds on all fast inputs – Up to 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks – High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144) • 100% interconnect matrix • High-speed arithmetic carry network – 1 ns ripple-carry delay per bit – 43 to 61 MHz 18-bit accumulators • Multiple independent clocks • Each input programmable as direct, latched, or registered • High-drive 24 mA output • I/O operation at 3.3 V or 5 V • Meets JEDEC Standard (8-1A) for 3.3 V ± 0.