Xilinx XC7Z030
The Zynq®-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device.| Part No. | XC7Z030 |
|---|---|
| Datasheet | XC7Z030 Download |
| Manufacturer |  Xilinx |
| Description | SoC |
| Buy | Stock & Price |
Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 Product Specification Zynq-7000 SoC First Generation Architecture The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) ARM Cortex-A9 Based Application Processor Unit (APU)
● 2.5 DMIPS/MHz per CPU
● CPU frequency: Up to 1 GHz
● Coherent multiprocessor support
● ARMv7-A architecture
● TrustZone® security
● Thumb®-2 instruction set
● Jazelle® RCT execution Environment Architecture
● NEON™ media-processing engine
● Single and double precision Vector Floating Point Unit (VFPU)
● CoreSight™ and Program Trace Macrocell (PTM)
● Timer and Interrupts
● Three watchdog timers
● One global timer
● Two triple-timer counters Caches
● 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
● 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
● Byte-parity s...
● 2.5 DMIPS/MHz per CPU
● CPU frequency: Up to 1 GHz
● Coherent multiprocessor support
● ARMv7-A architecture
● TrustZone® security
● Thumb®-2 instruction set
● Jazelle® RCT execution Environment Architecture
● NEON™ media-processing engine
● Single and double precision Vector Floating Point Unit (VFPU)
● CoreSight™ and Program Trace Macrocell (PTM)
● Timer and Interrupts
● Three watchdog timers
● One global timer
● Two triple-timer counters Caches
● 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
● 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
● Byte-parity s...
