XCR22LV10 Overview
The XCR22LV10 is the first SPLD to bine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the bination of...
XCR22LV10 Key Features
- Industry's first TotalCMOS™ SPLD
- both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and high spee
- Static current of less than 45 µA
- Dynamic current substantially below that of peting devices
- Pin-to-pin delay of only 10 ns True Zero Power device with no turbo bits or power down schemes Function/JEDEC map patibl
- 24-pin TSOIC-uses 93% less in-system space than a 28-pin PLCC
- 24-pin SOIC
- 28-pin PLCC with standard JEDEC pinout Available in mercial and industrial operating ranges Supports mixed voltage syste
- Functional Description