Datasheet Summary
XCR3032XL 32 Macrocell CPLD
0 14
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
Features
- -
- -
- Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O) Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power™ (FZP) CMOS design technology Advanced system Features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23...