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XCR3064XL-6PC44C - XCR3064XL 64 Macrocell CPLD

Description

The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of four function blocks provide 1,500 usable gates.

Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.

Features

  • Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages.
  • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five la.

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Datasheet preview – XCR3064XL-6PC44C

Datasheet Details

Part number XCR3064XL-6PC44C
Manufacturer Xilinx
File Size 96.12 KB
Description XCR3064XL 64 Macrocell CPLD
Datasheet download datasheet XCR3064XL-6PC44C Datasheet
Additional preview pages of the XCR3064XL-6PC44C datasheet.

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0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.6) January 8, 2002 Product Specification Features • • • • • Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per function block Excellent pin retention during design changes Full IEEE Standard 1149.
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