Datasheet Summary
APPLICATION NOTE
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
0 14-
DS035 (v1.2) August 10, 2000
Product Specification
Features
- -
- Industry's first TotalCMOS™ PLD
- both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed 3V, In-System Programmable (ISP) using a JTAG interface
- On-chip supervoltage generation
- ISP mands include: Enable, Erase, Program, Verify
- Supported by multiple ISP programming platforms
- 4-pin JTAG interface (TCK, TMS, TDI, TDO)
- JTAG mands include: Bypass, Idcode High-speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 µA 5V tolerant I/Os to...