Datasheet Summary
XCR3256XL 256 Macrocell CPLD
0 14
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
Features
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- - 7.5 ns pin-to-pin logic delays System frequencies up to 140 MHz 256 macrocells with 6,000 usable gates Available in small footprint packages
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- - 144-pin TQFP (116 user I/O pins) 208-pin PQFP (160 user I/O) 280-ball CS BGA (160 user I/O) Ultra low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five metal layer reprogrammable process FZP™ CMOS design technology In-system programming Input registers Predictable timing model Up to 23 clocks available per logic block Excellent pin retention during design changes Full IEEE Standard...