Xilinx XCR3256XL
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.| Part No. | XCR3256XL |
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| Datasheet | XCR3256XL Download |
| Manufacturer |  Xilinx |
| Description | 256 Macrocell CPLD |
| Buy | Stock & Price |
FEATURES
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● 7.5 ns pin-to-pin logic delays System frequencies up to 140 MHz 256 macrocells with 6,000 usable gates Available in small footprint packages
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● 144-pin TQFP (116 user I/O pins) 208-pin PQFP (160 user I/O) 280-ball CS BGA (160 user I/O) Ultra low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five metal layer reprogrammable process FZP™ CMOS design technology In-system programming Input registers Predictable timing model Up to 23 clocks available per logic block Excellent pin retention during design changes Full IEEE Standard 1149.1 boundary-scan (JTAG) Four global clocks Eight product term control terms per logic block
DESCRIPTION
A total of 16 logic blocks provide 6,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz. TotalCMOS™ Design Technique for Fast Zero Power Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach.
