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XCR3256XL - 256 Macrocell CPLD

Description

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of 16 logic blocks provide 6,000 usable gates.

Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz.

Features

  • 7.5 ns pin-to-pin logic delays System frequencies up to 140 MHz 256 macrocells with 6,000 usable gates Available in small footprint packages.
  • 144-pin TQFP (116 user I/O pins) 208-pin PQFP (160 user I/O) 280-ball CS BGA (160 user I/O) Ultra low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five metal layer reprogrammable process FZP™ CMOS design.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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0 R XCR3256XL 256 Macrocell CPLD 0 14 DS013 (v1.2) May 3, 2000 Preliminary Product Specification Features • • • • 7.5 ns pin-to-pin logic delays System frequencies up to 140 MHz 256 macrocells with 6,000 usable gates Available in small footprint packages • • • • • • • • 144-pin TQFP (116 user I/O pins) 208-pin PQFP (160 user I/O) 280-ball CS BGA (160 user I/O) Ultra low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five metal layer reprogrammable process FZP™ CMOS design technology In-system programming Input registers Predictable timing model Up to 23 clocks available per logic block Excellent pin retention during design changes Full IEEE Standard 1149.
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