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XCR3384XL - 384 Macrocell CPLD

Description

The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of 24 function blocks provide 9,600 usable gates.

Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.

Features

  • Lowest power 384 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 384 macrocells with 9,600 usable gates Available in small footprint packages - 144-pin TQFP (118 user I/O) - 208-pin PQFP (172 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (220 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process.

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Other Datasheets by Xilinx (now AMD)

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XCR3032XL-10PC44C XCR3032XL 32 Macrocell CPLD
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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0 R XCR3384XL: 384 Macrocell CPLD 0 14 DS024 (v1.3) August 10, 2001 Advance Product Specification Features • • • • • Lowest power 384 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 384 macrocells with 9,600 usable gates Available in small footprint packages - 144-pin TQFP (118 user I/O) - 208-pin PQFP (172 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (220 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.
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