Datasheet4U Logo Datasheet4U.com

XCR3512XL - 512 Macrocell CPLD

Description

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.

A total of 32 function blocks provide 12,800 usable gates.

Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz.

Features

  • Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Xilinx (now AMD)

Part Number Description
XCR3032 32 Macrocell CPLD
XCR3032XL-10CS48C XCR3032XL 32 Macrocell CPLD
XCR3032XL-10CS48I XCR3032XL 32 Macrocell CPLD
XCR3032XL-10PC44C XCR3032XL 32 Macrocell CPLD
XCR3032XL-10PC44I XCR3032XL 32 Macrocell CPLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
0 R XCR3512XL: 512 Macrocell CPLD 0 14 DS081 (v1.2) September 4, 2001 Advance Product Specification Features • • • • • Lowest power 512 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 127 MHz 512 macrocells with 12,800 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - FZP™ CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.
Published: |