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XCR5032 - 32 Macrocell CPLD

Description

The XCR5032 CPLD (Complex Programmable Logic Device) is the first in a family of CoolRunner™ CPLDs from Xilinx.

These devices combine high speed and zero power in a 32 macrocell CPLD.

Features

  • in a full 3V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 6 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA s.

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Datasheet preview – XCR5032

Datasheet Details

Part number XCR5032
Manufacturer Xilinx
File Size 384.55 KB
Description 32 Macrocell CPLD
Datasheet download datasheet XCR5032 Datasheet
Additional preview pages of the XCR5032 datasheet.

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Full PDF Text Transcription

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APPLICATION NOTE 0 R XCR5032: 32 Macrocell CPLD 0 14* DS045 (v1.1) February 10, 2000 Product Specification devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Xilinx also offers the high speed XCR3032 CPLD that offers these features in a full 3V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 6 ns PAL path with five dedicated product terms per output.
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