XCR5064
Key Features
- Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 µA 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Up to 12 clocks with programmable polarity at every macrocell 5V, In-System Programmable (ISP) using a JTAG interface - On-chip supervoltage generation - ISP mands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG mands include: Bypass, Idcode Support for plex asynchronous clocking Innovative XPLA™ architecture bines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI pliant Advanced 0.5µ E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each
