Xilinx XCR5064
the XCR5064C offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLDz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique.| Part No. | XCR5064 |
|---|---|
| Datasheet | XCR5064 Download |
| Manufacturer |  Xilinx |
| Description | 64 Macrocell CPLD with Enhanced Clocking |
| Buy | Stock & Price |
FEATURES
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● Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 7.5 ns Ultra-low static power of less than 100 µA 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Up to 12 clocks with programmable polarity at every macrocell 5V, In-System Programmable (ISP) using a JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms - Four pin JTAG interface (TCK, TMS, TDI, TDO) - JTAG commands include: Bypass, Idcode Support for complex asynchronous clocking Innovative XPLA™ architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced...
