XCR5064 Overview
APPLICATION NOTE 0 R XCR5064C: 64 Macrocell CPLD with Enhanced Clocking 0 14 DS044 (v1.1) February 10, 2000 Product Specification speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR5064C offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for `turbo bits' or other power down schemes.
XCR5064 Key Features
- Industry's first TotalCMOS™ PLD
- both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high