XPLA3
XPLA3 is CPLD manufactured by Xilinx.
Features
- -
- - Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture bines high speed with extreme flexibility Based on industry's first Total CMOS™ PLD
- both CMOS design and process technologies Advanced 0.35µ five metal layer E2CMOS process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
- Full Boundary Scan Test (IEEE 1149.1) Ultra-low static power of less than 100 µA Simple deterministic timing model Support for plex asynchronous clocking
- 16 product term clocks and four local control term clocks per logic block
- Four global clocks and one universal control term clock per device Excellent pin retention during design changes 5V tolerant I/O pins Input register set up time of 1.7 ns Logic expandable to 48 product terms High-speed pin-to-pin delays of 5.0 ns Slew rate control per macrocell 100% routable Security bit prevents unauthorized access Supports hot-plugging capability Design entry/verification using Xilinx or industry standard CAE tools Innovative Control Term structure provides:
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock enable control per macrocell Four output enable controls per logic block Foldback NAND for synthesis optimization Global 3-state which facilitates "bed of nails" testing Available in Chip-scale BGA, and QFP packages mercial and extended voltage industrial grades Pin patible with existing Cool Runner low-power family devices
Family Overview
The Cool Runner XPLA3 (e Xtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast Zero Power (FZP) design technology that bines low power and high speed. With this design technique, the XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously...
