ZL30101 Overview
The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable...
ZL30101 Key Features
- Supports Telcordia GR-1244-CORE Stratum 3
- Supports G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
- Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
- Simple hardware control interface
- Accepts two input references and synchronizes to any bination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz in
- Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz & 8.192 MHz or 32.768 MHz & 65.
- Hitless reference switching between any bination of valid input reference frequencies
- Provides 5 styles of 8 kHz framing pulses
- Holdover frequency accuracy of 1 x 10-8
- Lock, Holdover and Out of Range indication
ZL30101 Applications
- Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs
- Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses