MSC220 Datasheet | Zarlink Semiconductor

Description The Xpress Flow Engine contains the switching data base interface and buffer management logic in order to do the switching decision making for unicast, multicast, and broadcast frames. Hardware assisted queue manager is incorporated to facilitate buffer management. It also provides a generic Management Bus interface to allow external processor to do initialization, learning, VLAN, and RMON support, etc. In addition, a Xpress Flow Bus interface block is responsible for municating with the Network Access Controllers through the Xpress Flow message passing protocol. t Full IP Switching ◊ ◊ t MAC Address Mapping Table Related ponents: t EA218E - 8-port 10Mbps Ethernet Access Controller t EA218 - 6-port 10 + 2-port 10/100 Ethernet Access Controller t EA234 - 4-port 10/100 Fast Ethernet © 1998 Vertex Networks, Inc. 1999 Rev. 4.5 - February Xpress Flow-2020 Series - Ethernet Switch Chipset Characteristics Continue t Built-in address to port resolution ◊ ◊ ◊ Embedded 32-bit HISC™ (High density Instruction Set Core) Processor Optimized architecture for switch applications Loadable firmware for easy upgrade ADDRESS MAPPING TABLE SC220 Xpress Flow Engine SC220 Xpress Flow...