MV1403 Datasheet | Zarlink Semiconductor

.. Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink./obsolete_products/ ADVANCE INFORMATION DS3046-2.1 PCM MACROCELL DEMONSTRATOR The MV1403 contains 8 PCM macrocells which can be configured so as to perform the mon channel signalling and error detection functions for a 2.048 Mbit 30 channel PCM transmission link, operating to the appropriate CCITT remendations. The MV1403 also allows access to all the macrocells individually and is implemented in GPS CMOS technology utilising the CLA60000 series gate array, offering high performance, low power and fast turn-round. The following macrocells are included in the MV1403. Timeslot Zero Transmitter - TXTSZ Timeslot Sixteen Transmitter - TXTS16 Cyclic Redundancy Check Generator - CRCGEN High Density Bipolar (HDB) 3 Encoder - HDB3EC Timeslot Zero Receiver - RXTSZ Timeslot Sixteen Receiver - RXTS16 Cyclic Redundancy Checker - CRCCHK High Density Bipolar (HDB) 3 Decoder - HDB3DC With the MV1403 set up to bine the internal macrocells, two demonstration modes are available, referred to as Transmit and Receive demonstration modes. In Transmit demonstration mode, timeslot zero sync word (including user data bits and optional CRC check bits), timeslot sixteen data and 30 voice channels are bined and transmitted as pseudo-ternary HDB3 encoded outputs. The Transmit demonstration mode can also be set to generate CRC multiframe data in accordance with CCITT Remendation G. 704. In Receive demonstration mode, the pseudo-ternary HDB3 inputs are decoded back to NRZ form and frame synchronisation is achieved by detection of the Frame Alignment signal in the ining data stream. This permits extraction of user data bits, timeslot sixteen data and voice channel data. An optional CRC mode generates CRC multiframe alignment and a cyclic redundancy check...