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MVA60000 MVA60000 Series
1.4 Micron CMOS MEGACELL ASICs
DS5499
ISSUE 3.1
March 1991
GENERAL DESCRIPTION Very large scale integrated circuits, requiring large RAM and ROM blocks, often do not suit even high complexity gate arrays, such as Zarlink Semiconductors' CLA60000 series. MVA60000 Megacell ASICs provide RAM, ROM, and PLA macros, optimised for minimum area, which are compiled to match system requirements exactly. Based on an advanced CMOS process using stacked contacts and vias to produce cells virtually 'transparent' to interconnection routing, MVA60000 allows systems up to 80,000 gates to be integrated on a single silicon chip. With ever-decreasing lifecycles many systems need a clear migration route to higher technology. MVA60000 designs are fully netlist compatible with 1.
MVA60000 Datasheet
