PDSP16318MC Datasheet | Zarlink Semiconductor

FEATURES s s s s s s s s s s Full 10MHz Throughout in FFT Applications Four Independent 16-bit I/O Ports 20-bit Addition or Accumulation Fully patible with PDSP16112 plex Multiplier On Chip Shift Structures for Result Scaling Overflow Detection Independent Three-State Outputs and Clock Enables for 2 Port 10MHz Operation 1.4 micron CMOS 500m W Maximum Power Dissipation 100 pin ceramic QFP Fig.1 Pin connections Rev Date NOTE MAR 1993 NOV 1998 Polyimide is used as an inter-layer dielectric and as glassivation. ORDERING INFORMATION PDSP16318/MC/GC1R (Ceramic QFP Package MIL STD 883 Screening) DELAY B SHIFT A REG C A SHIFT B REG B REG D Fig.2 PDSP16318 simplified block diagram PDSP16318 MC CEA DEL ASR S2:0 OEC 16 A A REG 8 CYCLE DELAY 20 B 20 SHIFT A 16 REG 16 D 20 MUX 20 CLK 20 MS MUX 20 REG CLR OVR A 16 SHIFT 16 B REG 16 B 20 REG 16 D Fig.2 Block diagram FUNCTIONAL DESCRIPTION The PDSP16318 is a Dual 20-bit Adder/Subtractor configured to supprt plex Arithmetic. The device may be used with each of the adders allocated to real or imaginary data (e.g. plex Conjugation), the entire device allocated to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of the adders configured as accumulators and allocated to real or imaginary data (plex Filters). Each of these modes ensures that a full 10MHz throughput is maintained through both adders, the first and last mode illustrating true plex operation, where both real and imaginary data is handled by the single device. Both Adder/Subtractors may be controlled independently via the ASR and ASI inputs. These controls permit A + B, A - B, B - A or pass A operations, where the A input to the Adder is derived from the input multiplexer. The CLR control line allows the clearing of both accumaltor registsers. The two multiplexers may be controlled via the MS inputs, to select either new input data, or fed-back data from the accumulator registers. The PDSP16318...