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SP5610 - 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER

Datasheet Summary

Description

The SP5610 is programmed from an I2C Bus.

Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format.

The synthesiser can either accept new data (write mode) or send data (read mode).

Features

  • J Complete 1.3GHz Single chip System J High Sensitivity RF Inputs J Programmable via I2C Bus J On Chip oscillator with 1kW negative resistance J Low power consumption (5V, 20mA) J Low Radiation J Phase Lock Detector J Varactor Drive Amp Disable J 5 Controllable Outputs J 5 Level ADC J Variable I2C BUS Address For Multi Tuner.

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Datasheet Details

Part number SP5610
Manufacturer Zarlink Semiconductor
File Size 430.16 KB
Description 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER
Datasheet download datasheet SP5610 Datasheet
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Full PDF Text Transcription

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FEBRUARY 1997 ADVANCE INFORMATION D.S. 3920 3.3 SP5610 1.3GHz BI–DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER (Supersedes edition in 1996 Media IC Handbook, HB4599–1.0) The SP5610 is a single chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device contains 1 addressable current limited output and 4 addressable bi–directional open collector ports one of which is a 3 bit ADC. The information on these ports can be read via the I2C BUS. The device has one fixed I2C BUS address and 3 programmable addresses, programmed by applying a specific input voltage to the P3 current limited output. This enables 2 or more synthesisers to be used in a system. FEATURES J Complete 1.
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