ZL50052 Datasheet | Zarlink Semiconductor

Features - 8,192 channel x 8,192 channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be bined to form a non-blocking switching matrix with 16 input streams and 16 output streams 4,096 channel x 4,096 channel non-blocking Backplane input to Local output stream switch 4,096 channel x 4,096 channel non-blocking Local input to Backplane output stream switch 4,096 channel x 4,096 channel non-blocking Backplane input to Backplane output switch 4,096 channel x 4,096 channel non-blocking Local input to Local output stream switch Backplane port accepts 8 input and 8 output STBUS streams with data rate of 32.768 Mbps Local port accepts 8 input and 8 output ST-BUS streams with data rate of 32.768 Mbps Exceptional input clock jitter tolerance (14 ns) Per-stream bit delay for Local and Backplane input streams Per-stream advancement for Local and Backplane output streams - - - - - - - Ordering Information ZL50052GAC 196 ball PBGA December 2003 - - - - - - - - - -40 ° C to +85 ° C Constant 2-frame throughput delay for frame integrity Per-channel high impedance output control for Local and Backplane streams Per-channel driven-high output control for Local and Backplane streams Per-channel message mode for Local and Backplane output streams Connection memory block programming for fast device initialization Automatic selection between ST-BUS and GCIBus operation Non-multiplexed Motorola microprocessor interface VDD_IO VDD_CORE VSS (GND) RESET BSTi0-7 Backplane Data Memories (4,096 channels) Local Interface LSTi0-7 Backplane Interface BSTo0-7 Backplane Connection Memory (4,096 locations) Local Connection Memory (4,096 locations) Local Interface LSTo0-7 BORS Local Data Memories (4,096 channels) LORS FP8i Input Timing Unit Output Timing Unit FP8o FP16o C8o C16o C8i Microprocessor Interface and Internal Registers Test Port VDD_PLL DS CS R/W A14-0 D15-0...