ZL50130 Datasheet | Zarlink Semiconductor

ZL50130 Ethernet Pseudo-Wires across a PSN Data Sheet Applications - Ethernet Pseudo-Wires across a Packet Switch Network Ordering Information ZL50130 PBGA -40°C to +85 °C System Interfaces - - - Flexible 32-bit host CPU interface (Motorola Power QUICC™ II patible) Dual address DMA transfer of packets to or from the CPU On-chip packet memory for self-contained operation Flexible, multi-protocol packet encapsulation, with support for IPv4/6, MPLS, L2TP, PWE3 Wire speed processing and forwarding of packets Packet sequencing and re-ordering where required Four classes of service with programmable priority mechanisms (WFQ and SP) Flexible classification of ining packets at layers 2, 3, 4 and 5 October 2004 Features Ethernet Pseudo-Wire Emulation Functions Supports the following functions for Ethernet Pseudo Wire emulation over the packet domain: - - - - Transports the plete Ethernet frame (less preamble and FCS) across the PSN Supports up to 127 point-to-point pseudo-wire links across the PSN VLAN priority field may be used to determine class of service on the PSN plies with the standards for Ethernet pseudowires proposed in the IETF’s PWE3 working group 3 x 100 Mbit/s MII interfaces Packet Processing Functions - - - - - Network Interfaces - Host Processor Interface Motorola Power QUICCTM II patible packet receive/classifier protocol engine task manager MAC packet transmit - add layer 2/3 headers memory management / on-chip packet memory Optional Off-chip Packet Memory 0-8 MBytes SSRAM Figure 1 - High Level Overview Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Packet Switched Network Interface 100 Mbit/s MII Host Processor Interface with DMA support Customer End Services 100 Mbit/s MII Description Data Sheet The ZL50130 is part of a range of highly functional bridging devices. It...