Description
The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment.
Features
- Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 77.76 MHz Provides a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supp.
ZL30406 Datasheet
