ZL30406 Datasheet | Zarlink

Features - - - - Meets jitter requirements of Telcordia GR-253CORE for OC-48, OC-12, and OC-3 rates Meets jitter requirements of ITU-T G.813 for STM16, STM-4 and STM-1 rates Provides four LVPECL differential output clocks at 77.76 MHz Provides a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz Provides a single-ended CMOS clock at 19.44 MHz Provides enable/disable control of output clocks Accepts a CMOS reference at 19.44 MHz 3.3 V supply Ordering Information ZL30406QGC 64 Pin TQFP ZL30406QGC1 64 Pin TQFP- - Pb Free Matte Tin -40° C to +85 ° C Trays Trays February 2005 Description The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30406 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-16, STM-4 and STM-1 rates. The ZL30406 accepts a CMOS patible reference at 19.44 MHz and generates four LVPECL differential output clocks at 77.76 MHz, a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz and a single-ended CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled. - - - - Applications - - SONET/SDH line cards Network Element timing cards C77o EN-A C77o EN-B OC-CLKo EN C77o ,C155o C19o, C38o, CML-P/N outputs OC-CLKo P/N C19i Frequency & Phase Detector 19.44MHz BIAS Reference & Bias circuit Loop Filter Output Interface Circuit C77o P/N-A C77o P/N-B C77o P/N-C C77o P/N-D C19o VDD GND FS1-2 C19o EN C77o EN-C C77o EN-D 15 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Data Sheet GND VCC1 VCC OC-CLKo N OC-CLKo P GND VCC2...