A4S12D40FTP Overview
All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The 512Mb DDR SDRAM achieves very high speed data rate up to 200MHz, and are suitable for main memory in puter systems.
A4S12D40FTP Key Features
- Vdd=Vddq=2.5V+0.2V(G6 Grade) -Vdd=Vddq=2.6V+0.1V(G5 Grade)
- Double data rate architecture
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS trans