A3R1GE4EGF - 1Gb DDRII SDRAM

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

Zentel

Datasheet Details

Part number	A3R1GE4EGF
Manufacturer	Zentel
File Size	1.64 MB
Description	1Gb DDRII SDRAM
Datasheet	A3R1GE4EGF Datasheet

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Full PDF Text Transcription

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A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp. Revision 1.0 Apr., 2010 Specifications • Density: 1G bits • Organization ⎯ 8M words × 16 bits × 8 banks (A3R1GE4EGF) • Package ⎯ 84-ball FBGA(μBGA) (A3R1GE4EGF) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.

Published: May 11, 2016 |