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A3R1GE4EGF - 1Gb DDRII SDRAM

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Zentel

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A3R1GE4EGF 1Gb DDRII SDRAM by Zentel - Datasheet Preview — Datasheet preview – A3R1GE4EGF

Datasheet Details

Part number	A3R1GE4EGF
Manufacturer	Zentel
File Size	1.64 MB
Description	1Gb DDRII SDRAM
Datasheet	A3R1GE4EGF Datasheet
Additional preview pages of the A3R1GE4EGF datasheet.

Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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Published: May 11, 2016 |