A3R56E40ABF Overview
A3R56E40ABF 256Mb DDRII Synchronous DRAM 256Mb DDRII SDRAM Specification A3R56E40ABF Zentel Electronics Corp. Revision 1.2 Dec., 2012 A3R56E40ABF 256Mb DDRII Synchronous DRAM Specifications Density: VDD, VDDQ = 1.8V ± 0.1V Data rate:.
A3R56E40ABF Key Features
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- On-Die-Termination for better signal quality
- /DQS can be disabled for single-ended