A3S28D40JTP - 128M Double Data Rate Synchronous DRAM

Product Overview

Zentel

Part number	A3S28D40JTP
Manufacturer	Zentel
File Size	533.07 KB
Description	128M Double Data Rate Synchronous DRAM
Datasheet	A3S28D40JTP Datasheet
Additional preview pages of the A3S28D40JTP datasheet.

A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

- VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - CAS latency - 2.0 / 2.5 / 3.0 (programmable) ; Burst length -.

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Published: Sep 1, 2015 |