A3S28D40JTP
Description
A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.
Key Features
- VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle
- All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK
- Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing)
- Clock Enable: CKE controls Power Down and Self Refresh
- Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle), or Active Power Down (row active in any bank)
