A3S64D40GTP - 64M Double Data Rate Synchronous DRAM

A3S64D40GTP is a 4-bank x 1,048,576-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

• - Vdd=VddQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - CAS latency - 2 / 2.5 / 3 (programmable) - Burst length - 2 / 4 /.