A3S64D40GTP
Description
A3S64D40GTP is a 4-bank x 1,048,576-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.
Key Features
- All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK
- Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing)
- Clock Enable: CKE controls Power Down and Self Refresh
- Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle), or Active Power Down (row active in any bank)
- Taking CKE HIGH provides Power Down exit or Self Refresh exit
