ZDV5128M16 Overview
Key Features
- 8n-bit prefetch architecture
- Fully differential clock inputs (CK,CK) operation
- Bi-directional differential data strobe (DQS,DQS)
- On chip DLL align DQ, DQS and DQS transition With CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable additive latency 0, CL-1, and CL-2 supported
- Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
- Programmable burst length 4/8 with both nibble sequential and interleave mode
- BL switch on the fly
