Z16C32SL1660 Datasheet | Zilog

PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z16C32 SL1660 ONLY IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER GENERAL DESCRIPTION The IUSC (Integrated Universal Serial Controller) is a single-channel multple protocol data munications device with on-chip dual-channel DMA. The integration of a highspeed serial munications channel with a high performance DMA facilitates higher data throughput than is possible with discrete serial/DMA chip binations. The buffer chaining capabilities bined with Features like character counters, frame status block and buffer termination at the end of the frame facilitate sophisticated buffer management that can significantly reduce CPU overhead. The IUSC is software configurable to satisfy a wide variety of serial munications applications. Offered at 20 Mbit/sec, its fast data transfer rate and multiple protocol support make it ideal for applications in todays dynamic environment of changing specifications and ever increasing speed. The many programmable Features allow the user to tune the device response to meet system requirements and adapt to future changes with software instead of redesigning hardware. The on-chip DMA channels allow high-speed data transfers for both the receiver and the transmitter. The device supports automatic status transfer through DMA and allows device initialization under DMA control. Each DMA channel can transfer data words in as little as three 50 ns clock cycles and can generate addresses patible with 32-, 24- or 16-bit memory ranges. The DMA channels may operate in any of four modes: single buffer, pipelined, array-chained, or linked-list. The array-chained and linkedlist modes reduce the problems with segmentation and reassembly of messages in systems. To prevent the DMA from holding bus mastership too long, mastership time may be limited by counting the absolute number of clock cycles, the number of bus transactions, or both. The CPU bus interface is designed for use with any...