Z5380 Datasheet | Zilog

FEATURES s s s s s Pin patible with the Industry Standard 5380 40-Pin DIP or 44-Pin PLCC Package Styles Low-Power CMOS Asynchronous Interface (Supports 1.5 MB/s) Direct SCSI Bus Interface with On-Board 48 m A Drivers s s s s s Supports Target and Initiator Roles Arbitration Support DMA or Programmed I/O Data Transfers Supports Normal or Block Mode DMA Memory or I/O Mapped CPU Interface GENERAL DESCRIPTION detects a bus condition that requires attention. It also The Z5380 SCSI (Small puter System Interface) consupports arbitration and reselection. The Z5380 has the troller is designed to implement the SCSI protocol as proper hand-shake signals to support normal and block defined by the ANSI X3.131-1986 standard, and is fully .. mode DMA operations with most DMA controllers availpatible with the industry standard 5380. It is capable able (Figure 2). of operating both as a Target and as an Initiator. Special high-current open-drain outputs enable the Z5380 to di Notes: rectly interface to, and drive, the SCSI bus. The Z5380 has All Signals with a preceding front slash, "/", are active Low, e.g., the necessary interface hook-ups which allows the system B//W (WORD is active Low); /B/W (BYTE is active Low, only). CPU to municate with it like any other peripheral device. The CPU can read from, or write to, the SCSI Power connections follow conventional descriptions below: registers which are addressed as standard or memorymapped I/Os (Figure 1). Connection Circuit Device The Z5380 increases the system performance by minimizing the CPU intervention in DMA operations which the SCSI controls. The CPU is interrupted by the SCSI when it Power Ground VCC GND VDD VSS PS97SCC0100 PS009101-0201 ZILOG Z5380 SCSI GENERAL DESCRIPTION (Continued) /DB7-/DB0, /DBP /ACK /ATN /BSY /MSG I//O C//D /REQ /RST /SEL 48 m A SCSI Transceivers /IOR /IOW /CS /RESET A2-A0 D7-D0 CPU BUS Interface Interface Control Logic Data Input Register Data Output Register DMA...