Z8000 Datasheet | Zilog

Features General Description - Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal OSCillator, baud rate generator, and Digital Phase-Locked Loop for clock recovery. - Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data encoding. - Asynchronous mode with five to eight bits and one, one and one-half, or two stop bits per character; programmable clock factor; break detection and generation; parity, overrun, and framing error detection. - Synchronous mode with internal or external character synchronization on one or two The Z8030 Z-SCC Serial munications Controller is a dual-channel, multi-protocol data munications peripheral designed for use with the Zilog Z-Bus. The Z-SCC functions as a serial-to-parallel, parallel-to-serial converter/controller. The Z-SCC can be softwareconfigured to satisfy a wide variety of serial April 1985 synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT preset to either Is or Os. - SDLC/HDLC mode with prehensive frame-level control, automatic zero insertion and deletion, I-field residue handling, abort generation and detection, CRC generation and checking, and SDLC Loop mode operation. - Local Loopback and Auto Echo modes. - 1.544M bit/second Tl digital trunk patible version available. munications applications. The device contains a variety of new, sophisticated internal functions including on-chip baud rate generators, Digital Phase-Locked Loops, and crystal oscillators that dramatically reduce the need for external logic. 2016-001,002 ADDRESS' DATA BUS AD, Tx DA } SERIAL AD, RIl OA _ _ DATA AD, TRx CA -} CHANNEL AD, RTx CA .--- CLOCKS AD, AD, CHANNEL AD, CONTROLS FOR MODEM, ADo DMA,OR As OTHER R/W es, } SERIAL _ _ DATA esc INTACK l EI l EO -IRTxes _... CHANNEL CLOCKS SYNCe WIREOB DTR/REQB Rl SB CHANNEL CONTROLS FDOMRAM,OORDEM, Z8030 else __ OTHER z- scc De DS CH- A CH- B ttt +5V GND...