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PECL_RX - CMOS PECL Receiver

General Description

The PECL_RX is a 3.3 V PECL differential line receiver featuring an operating frequency up to 311 MHz (622 Mb/s) and accepting standard F100K levels (referred to the positive supply).

The PECL_RX accepts (750 mV) differential input signals and translates them to CMOS output levels.

Key Features

  • ! ! ! ! ! ! ! ! ! PECL_RX area: 0.1 mm2, size: x = 300 µm y = 340 µm.

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Datasheet Details

Part number PECL_RX
Manufacturer austriamicrosystems AG
File Size 316.04 KB
Description CMOS PECL Receiver
Datasheet download datasheet PECL_RX Datasheet

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Full PDF Text Transcription (Reference)

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ANALOG IP BLOCK PECL_RX - CMOS PECL Receiver DATA SHEET PROCESS C35B3 (0.35um) DESCRIPTION The PECL_RX is a 3.3 V PECL differential line receiver featuring an operating frequency up to 311 MHz (622 Mb/s) and accepting standard F100K levels (referred to the positive supply). The PECL_RX accepts (750 mV) differential input signals and translates them to CMOS output levels. With the companion line driver (PECL_TX ) it can be used for high speed applications. The cell PECL_RX requires the PERXBIAS cell for biasing. PERXBIAS can drive up to 3 PECL_RX cells. An external voltage reference must be used. The PECL_RX can be set in power down mode. www.DataSheet4U.com FEATURES ! ! ! ! ! ! ! ! ! PECL_RX area: 0.1 mm2, size: x = 300 µm y = 340 µm PERXBIAS size: x = 382 µm y = 375 µm 3.