EV10AQ190
Description
The Quad ADC is made up of four 10-bit ADC cores which can be considered independently (4channel mode) or grouped by 2 x 2 cores (2-channel mode with the ADCs interleaved two by two) or 1-channel mode (where all four ADCs are all interleaved together). All four ADCs are clocked by the same external input clock signal and controlled via an industry standard SPI (Serial Peripheral Interface).
Key Features
- 1.25 Gsps Sampling Rate in 4-channel mode
- 2.5 Gsps Sampling Rate in 2-channel mode
- 5 Gsps Sampling Rate in 1-channel mode
- Channel Mode Selection
- Selectable bandwidth (2 available settings)
- Gain, Offset, Phase Control
- Standby Mode (full or partial)
- Binary or Gray Coding Selection
- ENOB = 8.8 bit, SFDR = 65 dBc, SNR = 56 dB, DNL = ±0.3 LSB, INL = ±1.5 LSB (Fin= 100 MHz)
- ENOB = 8.5 bit, SFDR = 63 dBc, SNR = 54 dB (Fin= 620 MHz)
