EV8AQ160 Description
The Quad ADC is constituted by four 8-bit ADC cores which can be considered independently (fourchannel mode) or grouped by two cores (two-channel mode with the ADCs interleaved two by two or one-channel mode where all four ADCs are all interleaved). All four ADCs are clocked by the same external input clock signal and controlled via an SPI (Serial Peripheral Interface). An analog multiplexer (cross-point switch) is...
EV8AQ160 Key Features
- Quad ADC with 8-bit Resolution
- 1.25 Gsps Sampling Rate in Four-channel Mode
- 2.5 Gsps Sampling Rate in Two-channel Mode
- 5 Gsps Sampling Rate in One-channel Mode
- Built-in four-by-four Crosspoint Switch
- 2.5 GHz Differential Symmetrical Input Clock Required
- ADC Master Reset (LVDS)
- Double Data Rate Output Protocol
- LVDS Output Format
- Digital Interface (SPI) with Reset Signal