Texas Instruments 54ACT11253
The 54ACT11253 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11253 is characterized for operation from – 40°C to 85°C.54ACT11253, 74ACT11253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A – D3110, MARCH 1988 – REVISED APRIL 1993
● Inputs Are TTL-Voltage Compatible
● 3-State Version of ′ACT11153
● Permits Multiplexing From N Lines to One Line
● Performs Parallel-to-Serial Conversion
● Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t
● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OR N PACKAGE (TOP VIEW) A1 B2 1Y 3 GND 4 2Y 5 1G 6 2G 7 2C3 8 16 1C0 15 1C1 14 1C2 13 1C3 12 VCC 11 2C0 10 2C1 9 2C2 54ACT11253 . . . FK PACKAGE (TOP VIEW) 1C2 1C3 NC V CC 2C0 description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.
● Inputs Are TTL-Voltage Compatible
● 3-State Version of ′ACT11153
● Permits Multiplexing From N Lines to One Line
● Performs Parallel-to-Serial Conversion
● Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
● Flow-Through Architecture Optimizes PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t
● EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OR N PACKAGE (TOP VIEW) A1 B2 1Y 3 GND 4 2Y 5 1G 6 2G 7 2C3 8 16 1C0 15 1C1 14 1C2 13 1C3 12 VCC 11 2C0 10 2C1 9 2C2 54ACT11253 . . . FK PACKAGE (TOP VIEW) 1C2 1C3 NC V CC 2C0 description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.