Datasheet Summary
- Inputs Are TTL-Voltage patible
- Generates Either Odd or Even Parity for
Nine Data Lines
- Cascadable for n-Bits Parity
- Flow-Through Architecture Optimizes
PCB Layout
- Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise t- EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
- 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs description
These universal, monolithic, 9-bit parity generators/checkers feature odd and even outputs to facilitate operation of either an odd or even parity application. The word-length capability is easily expanded...